Efficiency of Priority Queue Architectures in FPGA

This paper presents a novel SRAM-based architecture of data structure that represents set multiple priority queues can be implemented in FPGA or ASIC. The proposed is based on shift registers, systolic arrays and SRAM memories. Such architecture, called MultiQueue, optimized for minimum chip area costs, which leads to lower energy consumption too. MultiQueue has constant time complexity, critical path length latency. Therefore, it highly predictable very suitable real-time systems was verified using simplified version UVM applying millions instructions with randomly generated input values. Achieved synthesis results are presented discussed. These show significant savings Look-Up Tables comparison existing solutions. More than 63% saved the instead queues.